Process and circuit arrangement to monitor physical parameters

ABSTRACT

In digital assemblies, the power supply voltage (U 1,  U 2 ) is monitored by a voltage monitoring module (RG 1,  RG 2 ). If the power supply voltage (U 1,  U 2 ) deviates from its setpoint range, the voltage monitoring module (RG 1,  RG 2 ) triggers a Reset of the entire digital assembly so as to prevent undefined logic states. A Power-On Reset signal is also produced when the power supply voltage (U 1,  U 2 ) is turned on, which has the effect that the digital assembly transitions to its operating state only after a defined time. For systems whose fail-safeness has certain minimum requirements placed on it, it is common to perform online diagnoses. It is desirable to also incorporate the voltage monitoring module (RG 1,  RG 2 ) into this online diagnosis. However, a test of the voltage monitor produces the same Power-On Reset as, for example turning on the power, and a “true” Power-On Reset is very difficult to differentiate from a “simulated” one. According to the invention, this is solved in that the monitoring is performed by at least two independent monitoring modules (RG 1,  RG 2 ) whose signals are linked through linking means (V 1,  V 2,  V 3,  V 4 ). This makes it possible to test the two independent monitoring modules (RG 1,  RG 2 ) independent of one another.

[0001] This invention pertains to a circuit arrangement and process to monitor physical parameters as well as a process to diagnose the circuit arrangement according to the invention, in particular for use in telecommunications equipment.

[0002] In digital assemblies, the power supply voltage is monitored through a voltage monitoring module. If the deviation of the power supply voltage from its setpoint reaches or exceeds a specified threshold value, the voltage monitoring module triggers a reset of the entire digital assembly, called a “Power-On Reset” below, so as to prevent any undefined logic states. Likewise, the entire digital assembly is provided with a Power-On Reset signal during the time the power supply voltage is turned on, which has the effect of keeping the digital assembly from transitioning to its operating state before a defined time or before the power supply voltage reaches a stable state.

[0003] For systems on whose fail-safeness certain minimum requirements are placed, it is common to perform a diagnosis or self-test at regular intervals and/or at the user's request during operation by means of built-in or external mechanisms. This is called “On-Line Diagnosis” in general. It is desirable to also incorporate the voltage monitoring module into this online diagnosis since it is precisely these modules that have a relatively high error probability, i.e., voltage monitoring modules have a relatively high FIT rate—Failure in Time Rate—(failure rate).

[0004] If as part of an online diagnosis, the voltage monitoring module is to be tested for correct functionality—i.e., by issuing a signal for this purpose to an appropriate signal input of the voltage monitoring module, a fluctuation in the power supply voltage is simulated, whereupon the voltage monitoring module produces an active Power-On Reset signal—this Power-On Reset signal likewise results in the resetting of the entire logic of an assembly as well as the processors contained therein. One of these processors will normally initiate the voltage monitoring test as one test step in the overall diagnosis procedure. However, since this test triggers the same Power-On Reset as is triggered when the device is turned on or during a strong fluctuation in the power supply voltage, it is very difficult for the processor to differentiate as to whether the assembly has just been turned on—a “true” Power-On Reset—or whether a test of the voltage monitoring module—a “simulated” Power-On Reset—had been responsible for the Power-On Reset.

[0005] Furthermore, the assembly initialization procedure directly follows a Power-On Reset. This initialization procedure or boot-up of the assembly after a Power-On Reset requires a not insignificant time frame, for example if large memory areas must be formatted or if large amounts of data are loaded from slow, non-volatile memories to the working memory.

[0006] Known solutions to this problem make use of a memory register, for example a static RAM memory, that is not erased by a pure Reset without an interruption in voltage, so as to differentiate between a “true” and a “simulated” Power-On Reset. This register is read after every Power-On Reset. There are three different cases:

[0007] The “test data template” exists in the memory register. This is the index for a “simulated” Power-On Reset as part of an online diagnosis that is continued at this point.

[0008] The “operating data template” exists in the memory register. This is the index for a “true” Reset that, for example, had been triggered by the voltage monitoring module due to a voltage fluctuation or by an assembly Reset.

[0009] Neither the “test data template” nor the “operating data template” exists in the memory register. This is the index for a “true” Power-On Reset after the power supply voltage is turned on. The processor now writes the “operating data template” to the register immediately and a normal assembly boot-up follows.

[0010] However, the differentiation of these three cases is not clear-cut all the time, due to physical effects, for example. For example, it has not been established how long a static RAM memory can maintain a data template without operating voltage. Thus, it is possible that the memory register can still contain the “operating data template” even though the assembly had been shut off for a longer period of time, in some cases for many minutes. Also, cases in which the “test data template” has just been written into the memory register and the Reset is triggered not by the test signal, but by a random voltage fluctuation, cannot be differentiated from cases in which the Reset is triggered by the test signal.

[0011] The objective of this invention is to improve the known processes and circuit arrangements to monitor physical parameters.

[0012] This objective is met by the features of patent claim 1 as well as claim 9.

[0013] Preferred embodiments are the object of the dependent claims.

[0014] According to the invention, the objective is met by a circuit arrangement that encompasses the following:

[0015] a first monitoring module RG1 to monitor at least one physical parameter U1, U2 with means to feed a signal to an evaluation circuit A when the monitored physical parameter U1, U2 deviates from its prescribed setpoint range, using a first output signal carrying means PON-RES1_L_I and with a first input signal carrying means PON-TEST1_L_O to input a first test signal, wherein the first test signal can produce the same change in state of the first monitoring module RG1 as is produced by a deviation of the monitored physical parameter from its setpoint range,

[0016] at least one other monitoring module RG2 to monitor the same physical parameter U1, U2, with means to feed a signal to the evaluation circuit A when the monitored physical parameter U1, U2 deviates from its prescribed setpoint range using other output signal carrying means PON-RES2_L_I and with other input signal carrying means PON-TEST2_L_O to input another test signal, wherein the other test signal can produce the same change in state of the other monitoring module RG2 as is produced by a deviation of the monitored physical parameter from its setpoint range,

[0017] a linking means V1 associated with the evaluation circuit A to link the signals fed through the first output signal carrying means PON_RES1_L_I and the other output signal carrying means PON_RES2_L_I to a resultant output signal PON_RES.

[0018] a first register means RTR associated with the evaluation circuit A to separately impress the first test signal onto the first input signal carrying means PON_TEST1_L_O and the second test signal onto the other input signal carrying means PON_TEST2_L_O, wherein the first register means RTR have a means to receive control information SI from control means S,

[0019] a second register means RIR associated with the evaluation circuit A that is connected to the first output signal carrying means PON_RES1_L_I and the other output signal carrying means PON_RES2_L_I and that has a means to transfer status information ZI to the control means S, the control means S associated with the evaluation circuit A, which encompass a means to evaluate status information ZI of the second register means RIR and a means to send control information SI to the first register means RTR.

[0020] An important advantage to this improved circuit arrangement is seen in that the monitoring is done by at least two independent monitoring modules RG1, RG2, so that by suitably selecting the linking means V1 of the evaluation circuit A, improved results can be attained in comparison with a circuit arrangement with only one monitoring module. In particular, it is possible to test the at least two independent monitoring modules RG1, RG2 independent of one another. This has a significant advantage in comparison to known solutions, in that the monitoring modules RG1, RG2, can be tested without having to trigger a Reset of the entire digital assembly, inclusive of the test logic or diagnostic logic.

[0021] To this end, it is advantageous that the signals of the monitoring modules are linked by means of a logical AND function—claim 2. This provides that only a state that is simultaneously established by the at least two monitoring modules RG1, RG2 can produce a valid Reset signal PON-RES for the digital assembly. However, an individual Reset signal by one of the monitoring modules as part of a test of this module does not trigger a Reset of the entire digital assembly.

[0022] In order to ensure the reliability of the evaluation circuit A and to detect failures, the evaluation circuit is incorporated into the self-test or diagnosis strategy of the superordinate unit—claims 3 and 4. In particular, for application-specific integrated circuits, or so-called ASIC's, processes and circuit implementations already exist in the form of built-in self tests that can be applied in a simple manner to the evaluation circuit A or sections of the evaluation circuit A—claim 4.

[0023] The circuit arrangement is suited advantageously for the monitoring of all physical parameters for which a Reset is required if a setpoint range is exceeded, for example for safety reasons or to prevent damage to the assembly, as well as to test the respective monitoring modules—claim 5.

[0024] For electronic assemblies, it is especially important to monitor electrical voltages, currents and temperatures—claim 6. In the case of monitoring electrical voltages, this c an prevent undefined logic states. If electrical currents and/or temperatures are monitored, damages caused by dissipation rates that are too high can be prevented by interrupting the current operation.

[0025] In electronic logic assemblies, there are usually two electrical voltages U1 and U2 powering the logic modules. According to claim 7, each of these two voltages is monitored by two monitoring modules.

[0026] For clocked electronic logic assemblies that operate with high clock frequencies, it is required that stable clock states be attained before activating the logic circuitry. According to claim 8, Reset signals with their own individual time characteristics are provided through different output signal carrying means, making possible a delayed removal of the Reset signal for the logic circuitry compared with the removal of the Reset signal for the clock-generating circuit sections.

[0027] Testing of the monitoring modules RG1, RG2 is carried out as follows:

[0028] in a first step, the first monitoring module RG1 is selected by the control means S,

[0029] in a second step, control information SI representing this selection is transferred to the first register means RTR,

[0030] in a third step, a test signal is transferred to the first monitoring module RG1 by means of the first input signal carrying means PON_TEST1_L_O,

[0031] in a fourth step, the status information ZI produced by the second register means RIR, which represents the signals of the output signal carrying means PON_RES1_L_I, PON_RES2_L_I, are received and then checked to see that the signal of the first output signal carrying means PON_RES1_L_I is a valid Reset signal and that the signal of the other output signal carrying means PON_RES2_L_I is an arbitrary valid signal different from the Reset signal,

[0032] in a fifth step, after a prescribed time frame beginning with the establishment of a valid Reset signal in step four, a check is performed by the control means S to see that the signal of the first output signal carrying means PON_RES1_L_I returns to an arbitrary valid signal different from the Reset signal,

[0033] steps one through five are repeated for all other monitoring modules RG2 accordingly.

[0034] This process helps to make advantageous use of the circuit arrangement according to the invention to test the at least two independent monitoring modules RG1, RG2 independent of one another. This provides a significant advantage in comparison to known solutions in that the monitoring modules RG1, RG2 can be tested without having to trigger a Reset of the entire digital assembly inclusive of the test logic or diagnostic logic.

[0035] Below, the circuit arrangement and the process according to the invention are explained in more detail as an exemplary embodiment with the help of two drawings.

[0036]FIG. 1 is a schematic representation of the circuit arrangement according to the invention in which the principle of the invention for monitoring a physical parameter, in this case an electrical voltage U1, is explained.

[0037]FIG. 2 is a schematic representation of an application of the circuit arrangement according to the invention to monitor two electrical voltages U1, U2.

[0038] In FIG. 1, an electrical voltage U1 to be monitored is shown, which is monitored by a first Power-On Reset generator RG1 (called voltage monitoring module RG1 below) and a second Power-On Reset generator RG2 (called voltage monitoring module RG2 below). When the voltage U1 deviates from a prescribed setpoint range, for example a nominal value of 5 volts with an allowable deviation of ±5% of the nominal value, the first voltage monitoring module RG1 produces a Reset signal on a first Reset line PON_RES1_L_I (stands for: Power-On_Reset1_Low-active_Input) that is an output line of the first voltage monitoring module RG1, and the second voltage monitoring module RG2 produces a Reset signal on a second Reset line PON_RES2_L_I (stands for: Power-On_Reset2_Low-active_Input) that is an output line of the second voltage monitoring module RG2.

[0039] The first voltage monitoring module RG1 has an input line PON_TEST1_L_O (stands for: Power-On_Test1_Low-active_Output), through which a first test signal can be input to the first voltage monitoring module RG1. Inputting the first test signal to the first voltage monitoring module RG1 causes the voltage monitoring module RG1 to perform a self-test, whereupon a valid Reset signal is issued from it on the first Reset line PON_RES1_L_I.

[0040] The second voltage monitoring module RG2 has an input line PON_TEST2_L_O (stands for: Power-On_Test2_Low-active_Output), through which a second test signal can be input to the second voltage monitoring module RG2. Inputting the second test signal to the second voltage monitoring module RG2 causes the voltage monitoring module RG2 to perform a self-test, whereupon a valid Reset signal is issued from it on the second Reset line PON_RES2_L_I.

[0041] In normal operating condition, i.e., the monitored voltage U1 lies within the prescribed setpoint range and no test signals are input through the input lines PON_TEST1_L_O, PON_TEST2_L_O to the voltage monitoring modules RG1, RG2, the outputs on the Reset lines PON_RES1_L_I, PON_RES2_L_I are signals that are different from a Reset signal. A common form of a signal different from a Reset signal on a Reset line is a steady high level representing the logic state “1”, whereas an active Reset signal is a low level representing the logic state “0”. This characteristic of a signal line is also called “low active”. The circuit arrangement according to the invention is, however, easily applicable to other signal forms on the Reset lines PON_RES1_L_I, PON-RES2_L_I.

[0042] The signals of the Reset lines PON_RES1_L_I, PON-RES2_L_I are input signals to an evaluation circuit A, whereas the signals of input lines PON_TEST1_L_O, PON-TEST2_L_O to the voltage monitoring modules RG1, RG2 are output signals from the evaluation circuit A.

[0043] The evaluation circuit A encompasses at least four elements according to the invention, wherein these four elements can be assembled in arbitrary combinations. These four elements are, individually

[0044] a linking circuit V1 that has as its input signal the signals of the first Reset line PON_RES1_L_I and the second Reset line PON_RES2_L_I, and as its output signal a Reset signal PON_RES resulting from them and generated using a logical AND function,

[0045] a Reset Index Register RIR that stores the signals of the first Reset line PON_RES1_L_I and the second Reset line PON_RES2_L_I temporarily, having an appropriate amount of memory for this purpose,

[0046] a Reset Test Register RTR that impresses separate signals onto the input lines PON_TEST1_L_O, PON_TEST2_L_O of the voltage monitoring modules RG1, RG2,

[0047] a control unit S that sends control information SI to the Reset Index Register RIR, reads out status information from the Reset Index Register RIR and controls the diagnosis of the voltage monitoring modules RG1, RG2.

[0048] The evaluation circuit A can, in the process, be a component of an assembly not shown. According to an advantageous further development of the circuit arrangement according to the invention, the evaluation circuit A is then incorporated into the diagnosis of the assembly. The control unit S then simultaneously controls, for example, other diagnostic control units that control the diagnosis of other functional units of the assembly, or the control unit S is controlled through a central control unit—not shown.

[0049] The evaluation circuit can be a component of a modern, application-specific integrated circuit—ASIC—which is not shown. In order to ensure the reliability of the evaluation circuit A and in the process that of the linking circuit V1 in particular, thus ensuring the high level of availability of the entire system, the evaluation circuit A is then completely or partially incorporated into the built-in self test process, BIST of the ASIC, well known in the art—which is not shown.

[0050] The process according to the invention to monitor the voltage U1 proceeds in the control unit S in the steps already described above.

[0051] With reference to FIG. 2, an application of the principles explained in connection with FIG. 1 of the present invention is illustrated for a memory assembly of a processor in a voice switching system.

[0052]FIG. 2 shows a first voltage U1 to be monitored and a second voltage U2 to be monitored, both of which are monitored by the first voltage monitoring module RG1 and the second voltage monitoring module RG2. In typical logic modules, the first voltage U1 can thus be monitored at a nominal value of 2.5 volts, the second voltage U2 can be monitored at a nominal value of 3.3 volts, and each of these with its respective first and second setpoint range.

[0053] Instead of only one Reset line each, the two voltage monitoring modules RG1, RG2 have two Reset lines each. If the first voltage U1 deviates from its respective first setpoint range, or if the second voltage U2 deviates from its respective second setpoint range, as well as when the power supply voltage is turned on, the first voltage monitoring module RG1 produces a Reset signal on the first Reset line PON_RES1_L_I and on a third Reset line PLL_RES1_L_I (stands for: PLL_Reset1_Low-active_Input), both of which are output lines of the first voltage monitoring module RG1. In the same manner, if the first voltage U1 deviates from its respective first setpoint range, or if the second voltage U2 deviates from its respective second setpoint range, the second voltage monitoring module RG2 produces a Reset signal on the second Reset line PON_RES2_L_I and on another Reset line that feeds signals to a total of three Reset lines: a fourth Reset line PLL_RES2_HSA_L_I (for: PLL_Reset2_HighSpeedClockDomainA_Low-active_Input), a fifth Reset line PLL_RES2_HSB_L_I (for: PLL_Reset2_HighSpeedClockDomainB_Low-active_Input), and a sixth Reset line PLL_RES2_75_L_I (for: PLL_Reset2_75 MHzClockDomain_Low-active_Input).

[0054] Due to circuit considerations, this exemplary embodiment requires the Reset signals to be split into a total of six Reset lines, as explained below. An ACMY (for: ASIC for Common Memory) module, for which the voltage monitoring and the generation of Power-On Reset signals is performed, is a highly complex ASIC that has, among other things, three different clock domains controlled by three separate phase control loops—PLL (for: phase locked loop)—which are not shown. The Reset signals for these PLL's are provided through the following four Reset lines: the third Reset line PLL_RES1_L_I, the fourth Reset line PLL_RES2_HSA_L_I, the fifth Reset line PLL_RES2_HSB_L_I, and the sixth Reset line PLL_RES2_75_L_I, whereas the first Reset line PON_RES1_L_I and the second Reset line PON_RES2_L_I provide the Reset signals for a logic circuit clocked by the three PLL's.

[0055] As soon as the clock states are stable, the logic circuit is switched to its operating state. In order to attain this, the logic circuit is activated later than the three PLL's by means of longer Reset signals on the first Reset line PON_RES1_L_I and the second Reset line PON_RES2_L_I compared to the Reset signals of the other four Reset lines.

[0056] The three PLL's are provided with different Reset signals. This provides advantages when testing the PLL since it becomes possible this way to separately test each PLL and thus the clock domains supplied by the PLL's. Effects on the circuit arrangement according to the invention only occur to the extent that the PLL Reset signal of the second voltage monitoring module RG2 feeds a total of three Reset lines: the fourth Reset line PLL_RES2_HSA_L_I, the fifth Reset line PLL_RES2_HSB_L_I, and the sixth Reset line PLL_RES2_75_L_I.

[0057] The first voltage monitoring module RG1 contains the first input line PON_TEST1_L_O, as explained already in connection with FIG. 1, through which the first test signal is input to the first voltage monitoring module RG1. Inputting the first test signal to the first voltage monitoring module RG1 causes the voltage monitoring module RG1 to perform a self-test, whereupon a valid Reset signal is issued from it to both the first Reset line PON-RES1_L_I and to the second Reset line PLL_RES1_L_I.

[0058] The first voltage monitoring module RG1 also has a third input line that is connected to a central Reset line MAN_RESET_L. This central Reset line MAN_RESET_L is connected to a device to manually trigger a Reset, for example. Inputting a valid Reset signal through the third input line connected to the central Reset line to the first voltage monitoring module RG1 causes a valid Reset signal to be issued to both the first Reset line PON-RES1_L_I and to the third Reset line PLL_RES1_L_I.

[0059] The second voltage monitoring module RG2 contains the second input line PON_TEST2_L_O, as already explained in connection with FIG. 1, through which the second test signal is input to the second voltage monitoring module RG2. Inputting the second test signal to the second voltage monitoring module RG2 causes the voltage monitoring module RG2 to perform a self-test, whereupon a valid Reset signal is issued from it to the second Reset line PON-RES2_L_I, the fourth Reset line PLL_RES2_HSA_L_I, the fifth Reset line PLL_RES2_HSB_L_I, and the sixth Reset line PLL_RES2_75_L_I.

[0060] The second voltage monitoring module RG2 also has a fourth input line that is connected to a central Reset line MAN_RESET_L. Inputting a valid Reset signal through the fourth input line connected to the central Reset line to the second voltage monitoring module RG2 causes a valid Reset signal to be issued to the second Reset line PON-RES2_L_I, the fourth Reset line PLL_RES2_HSA_L_I, the fifth Reset line PLL_RES2_HSB_L_I, and the sixth Reset line PLL_RES2_75_L_I.

[0061] The six Reset lines mentioned are input lines to the ACMY SIC, of which only the elements required for voltage monitoring and their testing are shown. The first input line PON_TEST1_L_O of the first voltage monitoring module RG1 and the second input line PON_TEST2_L_O of the second voltage monitoring module RG2 are output lines of the ACMY ASIC.

[0062] The six Reset lines are connected as follows within the ACMY ASIC to four linking elements, which then provide four resultant Reset signals:

[0063] the signal from the first Reset line PON_RES1_L_I and the signal from the second Reset line PON_RES2_L_I are linked in the first linking element V1 to the first resultant Reset signal PON_RES.

[0064] the signal from the third Reset line PLL_RES1_L_I and the signal from the fourth Reset line PLL_RES2_HSA_L_I are linked in a second linking element V2 to a second resultant Reset signal PLL_RES1.

[0065] the signal from the third Reset line PLL_RES1_L_I and the signal from the fifth Reset line PLL_RES2_HSB_L_I are linked in a third linking element V3 to a third resultant Reset signal PLL_RES2.

[0066] the signal from the third Reset line PLL_RES1_L_I and the signal from the sixth Reset line PLL_RES2_75_L_I are linked in a fourth linking element V4 to a fourth resultant Reset signal PLL_RES3.

[0067] Also, the six Reset lines are connected to the inputs of the Reset Index Register RIR within the ACMY ASIC, which has available six inputs, accordingly, and a larger number of memory locations, accordingly, than compared to FIG. 1. This is schematically represented in FIG. 2. The Reset Index Register is connected to control unit S as in FIG. 1, which is not shown in detail in FIG. 2.

[0068] The output lines from the ACMY ASIC (the first input line PON_TEST1_L_O and the second input line PON_TEST2_L_O) are connected to the Reset Test Register RTR from FIG. 1 within the ACMY ASIC—not shown. The Reset Test Register RTR is connected to control unit S—not shown.

[0069] The test procedure for the circuit arrangement according to FIG. 2 corresponds to that described for the circuit arrangement according to FIG. 1, with modifications in steps four and five. The modifications pertain to the circumstance that the circuit arrangement according to FIG. 2 has two Reset lines for the first voltage monitoring module RG1 and four Reset lines for the second voltage monitoring module RG2. Accordingly, in steps four and five of the procedure, two and four Reset lines must be taken into account which return, at the end of different time frames, to an arbitrary valid signal that is different from the Reset signal, i.e., in step five different time frames must be provided for different Reset lines of the same module.

[0070] The linking elements V1, V2, V3, and V4 used in the preferred exemplary embodiment implement the logical AND function to valid Reset signals. Since valid Reset signals can be represented by the logical state “0”, for example in case of low-active signal lines, a circuit implementation must be selected that is tailored, accordingly, to the existing input signals and to the desired output signals. Procedures for designing logic circuits and circuit arrangements to implement logical functions, for example for low-active logic circuits, are well-known in the art, so that this invention can be tailored according to specific circumstances without a problem. 

1. A circuit arrangement to monitor physical parameters (U1, U2), encompassing: a first monitoring module (RG1) to monitor at least one physical parameter (U1, U2) with means to feed a signal to an evaluation circuit (A) when the monitored physical parameter (U1, U2) deviates from its prescribed setpoint range using a first output signal carrying means (PON-RES1_L_I) and with a first input signal carrying means (PON-TEST1_L_O) to input a first test signal, wherein the first test signal can produce the same change in state of the first monitoring module (RG1) as is produced by a deviation of the monitored physical parameter from its setpoint range, at least one other monitoring module (RG2) to monitor the same physical parameter (U1, U2), with means to feed a signal to the evaluation circuit (A) when the monitored physical parameter (U1, U2) deviates from its prescribed setpoint range, using other output signal carrying means (PON-RES2_L_I) and with other input signal carrying means (PONTEST2_L_O) to input another test signal, wherein the other test signal can produce the same change in state of the other monitoring module (RG2) as is produced by a deviation of the monitored physical parameter from its setpoint range, a linking means (V1) associated with the evaluation circuit (A) to link the signals fed through the first output signal carrying means (PON_RES1_L_I) and the other output signal carrying means (PON_RES2_L_I) to a resultant output signal (PON_RES), a first register means (RTR) associated with the evaluation circuit (A) to separately impress the first test signal onto the first input signal carrying means (PON_TEST1_L_O) and the second test signal onto the other input signal carrying means (PON_TEST2_L_O), wherein the first register means (RTR) has a means to receive control information (SI) from a control means (S), a second register means (RIR) associated with the evaluation circuit (A) that is connected to the first output signal carrying means (PON_RES1_L_I) and the other output signal carrying means (PON_RES2_L_I) and that includes a means to transfer status information (ZI) to the control means (S), the control means (S) associated with the evaluation circuit (A), which encompass means to evaluate status information (ZI) from the second register means (RIR) and means to send control information (SI) to the first register means (RTR).
 2. A circuit arrangement according to claim 1, characterized in that the logic means (V1) is a gate that implements the logical AND function.
 3. A circuit arrangement according to one of claims 1 or 2, characterized in that the evaluation circuit (A) is part of an assembly, wherein the evaluation circuit (A) is a component of a diagnosis strategy of the assembly.
 4. A circuit arrangement according to one of claims 1 or 2, characterized in that the evaluation circuit (A) is a part of an application-specific integrated circuit—ASIC—, wherein the evaluation circuit (A) is included in the integrated self-test—Built-In Self Test, BIST—of the ASIC.
 5. A circuit arrangement according to one of claims 1 through 4, characterized in that the at least one monitored physical parameter (U1, U2) is an arbitrary selection of physical parameters which produce a reset signal when they deviate from a prescribed setpoint range.
 6. A circuit arrangement according to one of claims 1 through 5, characterized in that the at least one monitored physical parameter (U1) is an arbitrary selection from the parameters electric voltage, electric current and temperature.
 7. A circuit arrangement according to one of claims 1 through 6, characterized in that the at least one monitored physical parameter is a selection of at least two electric voltages (U1, U2) that are each monitored by both monitoring modules (RG1, RG2).
 8. A circuit arrangement according to one of claims 1 through 7, characterized in that the monitoring modules (RG1, RG2) each have a number of output signal carrying means (PON_RES1_L_I, PLL_RES1_L_I, PON_RES2_L_I, PLL_RES2_HSA_L_I, PLL_RES2_HSB_L_I, PLL_RES2_75_L_I), wherein each of the signals transferred through the numerous output signal carrying means of the same monitoring module (RG1, RG2) has its own time characteristics.
 9. A process to monitor at least one physical parameter (U1), according to which the physical parameter (U1) is monitored by a first monitoring module (RG1), wherein a signal is supplied by the first monitoring module (RG1) through a first output signal carrying means (PON_RES1_L_I) to an evaluation circuit (A) when the monitored physical parameter (U1) deviates from its prescribed setpoint range, a first test signal is input to the first monitoring module (RG1) through a first input signal carrying means (PON_TEST1_L_O), wherein the first test signal causes the same change in state of the first monitoring module (RG1) as would be caused by a deviation of the monitored physical parameter from its setpoint range, the physical parameter (U1) is monitored by at least one other monitoring module (RG2), wherein a signal is supplied by the other monitoring module (RG2) through other output signal carrying means (PON_RES2_L_I) to the evaluation circuit (A) when the monitored physical parameter (U1) deviates from its prescribed setpoint range, a second test signal is input to the other monitoring module (RG2) through other input signal carrying means (PON_TEST2_L_O), wherein the second test signal causes the same change in state of the other monitoring module (RG2) as would be caused by a deviation of the monitored physical parameter from its setpoint range, the signals fed to the evaluation circuit (A) through the first output signal carrying means (PON_RES1_L_I) and the other output signal carrying means (PON_RES2_L_I) are linked by linking means (V1), which are a component of the evaluation circuit A, to a resultant output signal (PON_RES), the first and the second test signal can be separately impressed onto the first input signal carrying means (PON_TEST1_L_O) and the other input signal carrying means (PON_TEST2_L_O) by the evaluation circuit (A) by means of first register means (RTR), wherein control information (SI) from the control means (S) is evaluated by the register means (RTR), signals from the first output signal carrying means (PON_RES1_L_I) and the other output signal carrying means (PON_RES2_L_I) are intercepted and status information (ZI) is transferred to the control means (S) through the evaluation circuit (A) by means of the second register means (RIR), the status information (ZI) of the second register means (RIR) is evaluated and control information (SI) is sent to the first register means (RTR) through the evaluation circuit (A) by means of the control means (S).
 10. A process according to claim 9, characterized in that a test of the monitoring modules (RG1, RG2) is carried out in that in a first step, the first monitoring module (RG1) is selected by the control means (S), in a second step, control information (SI) representing this selection is transferred to the first register means (RTR), in a third step, the first test signal is transferred to the first monitoring module (RG1) means of the first input signal carrying means (PON_TEST1_L_O), in a fourth step, the status information (ZI) produced by the second register means (RIR), which represents the signals of the output signal carrying means (PON_RES1_L_I), (PON_RES2_L_I), are received and then checked to see that the signal of the first output signal carrying means (PON_RES1_L_I) is a valid Reset signal and that the signal of the other output signal carrying means (PON_RES2_L_I) is an arbitrary valid signal different from the Reset signal, in a fifth step, after the expiration of a prescribed time frame beginning with the establishment of a valid Reset signal in step four, the control means (S) checks to see that the signal of the first output signal carrying means (PON_RES1_L_I) returns to an arbitrary valid signal different from the Reset signal, steps one through five are repeated for all other monitoring modules RG2 accordingly.
 11. A process according to one of claims 9 or 10, characterized in that the signals fed to the evaluation circuit (A) through the first output signal carrying means (PON_RES1_L_I) and the other output signal carrying means (PON_RES2_L_I) are linked according to the logical AND function in the linking means (V1).
 12. A process according to one of claims 9 to 1 [sic], characterized in that the evaluation circuit (A) is encompassed by a diagnosis strategy of an assembly containing the evaluation circuit (A) as a component.
 13. A process according to one of claims 9 to 11, characterized in that the evaluation circuit (A) is encompassed by a process for an integrated self-test—Built-In Self Test, BIST—of an application-specific integrated circuit—ASIC—containing the evaluation circuit (A) as a component.
 14. A process according to one of claims 9 through 13, characterized in that the at least one monitored physical parameter (U1) is made up of an arbitrary selection of physical parameters for which a reset signal is produced in case of a deviation from the prescribed setpoint range.
 15. A process according to one of claims 9 through 14, characterized in that the at least one monitored physical parameter (U1) is formed from an arbitrary selection from the parameters electric voltage, electric current and temperature.
 16. A process according to one of claims 9 through 15, characterized in that the at least one monitored physical parameter is formed from a selection of at least two electric voltages (U1, U2), each of which is monitored by both monitoring modules (RG1, RG2).
 17. A process according to one of claims 9 through 16, characterized in that signals are output by each of the monitoring modules (RG1, RG2) by means of a number of output signal carrying means (PON_RES1_L_I, PLL_RES1_L_I, PON_RES2_L_I, PLL_RES2_HSA_L_I, PLL_RES2_HSB_L_I, PLL_RES2_75_L_I), wherein each of the signals transferred through the numerous output signal carrying means of the same monitoring module (RG1, RG2) has its own time characteristics. 